At the recent RISC-V Summit organized by RISC-V International, its president Calista Redmond had a more blunt message: RISC-V is inevitable. In fact, she said, RISC-V will end up with the best CPUs, the best software to run on them, and the best ecosystem of any microprocessor core family.
SiFive CEO Patrick Little provided a year-long update on the company’s progress. A notable milestone was the partnership with MicroChip that won the Jet Propulsion Laboratory (JPL)/NASA design of the next-generation space computer, the HPSC.
The goal of the HPSC project is to define a computer that is 100 times more powerful than previous space computers. HPSC needs to be based on a long-lived ISA that NASA can rely on for the next 10-20 years, and RISC-V is considered such an instruction set. Previous space computers used the PowerPC ISA.
Andes was one of the first CPU IP vendors to embrace RISC-V. The company has been steadily building out a series of low-end CPU cores and is now adding vector extensions. Andes announced a new high-end CPU core called the AX65 with a 13-stage pipeline and out-of-order execution.
RISC-V has now jumped into the first year of high-performance computing. In the field of RISC-V high-performance computing, many innovative companies have planned to release similar 64-core high-performance server-class processors in 2023, which will be the next exciting milestone for RISC-V.
However, the application of RISC-V in high-performance computing still faces some urgent problems. According to Wang Junhui, co-founder and chief operating officer of Pengfeng Technology, the RISC-V system needs to build a set of mathematical computing libraries to support the application of RISC-V in high-performance computing, and ensure calculation accuracy, calculation efficiency and source code level security controllable.
Looking at RISC-V, due to its relatively short birth time, RISC-V is still actively building relevant compilers, development tools, software development environments and other ecological elements in the Chinese local market. In addition, most of the early development of RISC-V was abroad, so international collaboration is crucial. In order for RISC-V to continue to develop in a healthy way, it is obvious that more ecological partners need to participate and cooperate. How to build a sustainable ecology is a core question for RISC-V.
From the perspective of architectural complexity, RISC-V itself is very simple, with only more than 40 basic instruction sets, plus dozens of other modular extension instructions, and its specification document is only 145 pages, while the “privileged architecture document” The length is only 91 pages. Because ARM is a closed instruction set architecture, all manufacturers cannot change chips based on the original design after adopting the ARM IP core. Enterprises can only adjust their own needs to cater to the ARM core. After years of development, the ARM instruction set has become extremely complex and cumbersome, and the corresponding architecture documents have thousands of pages. This has also led to the fact that the research and development threshold of ARM processors is much higher than that of RISC-V.
Ten years of growth, the number of RISC-V CPUs has increased a lot
At present, there are already international manufacturers planning to introduce RISC-V into the HPC field. Ventana Micro Systems has announced its Veyron V1 chip, which it says offers comparable performance to chips based on x86 and Arm architectures.
The chip has up to 16 cores and can be paired with up to 12 other chips in a cluster for a total of 192 cores. Each core will run at up to 3.6GHz, and the chips will be manufactured using TSMC’s 5nm process. The chip has 48MB of shared L3 cache and supports CXL2.0 interconnect.
Regarding the software challenge of RISC-V in the development of high-performance fields, Wu Yanjun, chief engineer of the Institute of Software, Chinese Academy of Sciences, pointed out that there are currently many core basic software that do not run well on the RISC-V platform. There may be a problem that the instruction set specification is not yet mature, but it is more that these basic software packages used to run on X86 and Arm. From the perspective of maintainers and communities, RISC-V has not yet been regarded as a Tier- 1 or First-Class-Citizen degree to treat. There are conceptual issues, investment issues, and commercial return issues.
Entry into data center and automotive applications will put more pressure on improving the reliability of RISC-V designs. Researchers at the Universities of Bologna and Modena in Italy and ETH Zurich have developed an open-source SoC based on RISC-V capable of running Linux at ultra-low power consumption. Researchers from the Barcelona Supercomputing Center in Spain also recently unveiled a vector processing acceleration engine that integrates RISC-V vector extensions.
We can see that at the beginning of this year, Intel, the dominant player in the X86 market, also joined the RISC-V Foundation and became a Premier Members member. Arm’s most important partner in the mobile market, Qualcomm, also joined the RISC-V camp early and became a Premier Members member. These all highlight the amazing charm of RISC-V.
