Recently, open source RISC-V has come into the spotlight again. Not long ago, Tencent joined the open source instruction set standard RISC-V International Association (RISC-V International). After companies and institutions such as Alibaba, Huawei, Ziguang Zhanrui, ZTE, Saifang Technology, and the Chinese Academy of Sciences, new Chinese members have ushered in the RISC-V camp.
From its humble beginnings in a lab at the University of California, Berkeley, it’s been more than a decade since RISC-V was born. This emerging instruction set architecture, which is often talked about and must be compared with X86 and Arm, is exerting its potential in more application scenarios such as the Internet of Things and the cloud, attracting many companies to deploy. IP manufacturer Imagination launched the first commercial RISC-V core in the summer of 2022 for system-on-chip (SoC) design; Intel announced in February 2022 that it has officially joined the RISC-V International Association and invested 400 million euros with the Spanish Supercomputing Center Cooperation, plans to develop a RISC-V-based supercomputing CPU within 10 years; Google will launch a new open source operating system for RISC-V chips.
RISC-V has now jumped into the first year of high-performance computing. In the field of RISC-V high-performance computing, many innovative companies have planned to release similar 64-core high-performance server-class processors in 2023, which will be the next exciting milestone for RISC-V.
However, the application of RISC-V in high-performance computing still faces some urgent problems. According to Wang Junhui, co-founder and chief operating officer of Pengfeng Technology, the RISC-V system needs to build a set of mathematical computing libraries to support the application of RISC-V in high-performance computing, and ensure calculation accuracy, calculation efficiency and source code level security controllable.
The first market for RISC-V cores was deep embedded designs from Nvidia and Western Digital. During a keynote address at the 2022 event, Qualcomm’s Manju Varma revealed that the company has been using RISC-V CPU cores in its chips since the Snapdragon 865, and has shipped more than 650 million RISC-V cores to date.
One of the keynotes came from a Google executive. The topic is porting the Android Open Source Project to RISC-V. Although Alibaba has an earlier port, this is an official Google project. While Android running on RISC-V is making good progress for evaluation and early development, Google has made it clear that it needs certain architectural features to become a more mainstream product. This could really open up the RISC-V market for consumer devices running Android, including smartphones.
According to Varma, Qualcomm has started using RISC-V as the microcontroller core inside its chips, starting with the Snapdragon 865 SoC in 2019. According to Varma, he helps drive Qualcomm’s CPU strategy and roadmap across the company’s entire product portfolio.
Varma said RISC-V, an emerging alternative to the proprietary instruction set Arm architecture, has opportunities in a range of devices that Qualcomm’s chips target, including wearables, smartphones, laptops and connected cars, among others. And Qualcomm is now using RISC-V microcontrollers in SoCs for PCs, mobile devices, wearables, connected cars, and augmented and virtual reality headsets. These microcontrollers perform low-level work in the background, such as managing the hardware.
As of now, Qualcomm has shipped more than 650 million RISC-V cores, making the RISC ISA “one of Qualcomm’s core technologies” and Qualcomm “one of the leaders in RISC-V implementation,” Varma said.
“Thanks to the thousands of contributors to the RISC-V community, we’ve made great strides in the specification,” said Mark Himelstein, CTO of RISC-V International. Ratification in Q1 2023. A major milestone this year is everyone’s work on RISC-V Profiles to enable compatible implementations and portability of RISC-V applications, helping to further drive RISC-V adoption. Another The one that stands out is the Crypto vector ISA extension, as it will provide implementers with a huge performance boost.”
2023 will be a turning point and a breakthrough point for RISC-V
These technical achievements were made possible through the collaboration of RISC-V members across 81 technical groups. More than 30 such teams will be added in 2022 alone, focusing on fast-growing markets for RISC-V such as security, system-on-chip infrastructure, automotive, and AI/ML.
Varma emphasized that the main advantage of RISC-V is that it receives functional contributions from various companies and organizations at various layers of the “value chain,” from ISAs and CPUs, to system software, to operating systems, to end-user applications. With RISC-V, there is an opportunity to define chip designs with “best-in-class performance, best-in-class power efficiency, and value-added features.” “These advantages also make RISC-V such a general-purpose basic instruction set architecture that can scale from low-end microcontrollers all the way to high-performance computing and everything in between, and it improves the efficiency of the entire industry” .